This is a senior individual contributor position in the analog IC design group at Canesta, reporting to the Analog Design Manager. The group designs our highly integrated and high performance breakthrough 3D Time of Flight image sensor chips using conventional CMOS technology. The position requires architectural and implementation planning, direct circuit design, presenting design reviews, supervising and simulating the physical implementation. The ideal candidate is a self starter, highly motivated engineer with excellent technical skills, used to working independently or as a key member of a small, fast moving design team.
Minimum Requirements
- BSEE or Equivalent, MSEE preferred.
- 5 years minimum experience in custom Analog IC PLL and clock recovery & distribution circuit design.
- Proven track record at each of the following stages in product development:
- Design partitioning, jitter analysis, signal integrity analysis.
- Detailed circuit design and simulation, layout parasitic extraction & package modeling.
- Supervision of layout activity and editing of critical sections or blocks, large scale clock & power distribution.
- Chip bringup, debug, and silicon evaluation.
Additional Desired Experience
- Architecture development and feasibility studies.
- Chip characterization, qualification and release to production.
- Design of semiconductor sensors, especially image sensors.
- Experience in efficient PLL & large circuit simulation.
Canesta Career ID# CO-09-109
